1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, to a bias circuit which generates a bias voltage in an analog circuit such as an operational amplifier. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-18388 filed on Jan. 27, 2004, which is herein incorporated by reference.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a bias circuit of the related art. This bias circuit includes a voltage generator 10 which outputs a bias voltage and a start-up circuit 20 which activates the voltage generator 10 in a manner in which the voltage generator 10 outputs a stable bias voltage.
The voltage generator 10 has a P-type conductive Metal Oxide Semiconductor (hereinafter referred to as the “PMOS”) transistor 11, a resistance element 12 and an N-type conductive Metal Oxide Semiconductor (hereinafter referred to as the “NMOS”) transistor 13 which are connected in series between a power supply voltage terminal Tcc and a ground voltage terminal Tss. The PMOS transistor 11 has a source electrode connected with the power supply voltage terminal Tcc, a drain electrode connected with a first node N1, and a gate electrode connected with a second node N2. The N MOS transistor 1 3 has a source electrode connected with the ground voltage terminal Tss, a drain electrode connected with the first node N1 through the resistance element 12, and a gate electrode connected with a third node N3. The drain electrode of the NMOS transistor 13 is also connected with the node N3. That is, the NMOS transistor is diode-connected. Also, the voltage generator 10 has a PMOS transistor 14, an NMOS transistor 15 and a resistance element 16 connected in series between the power supply voltage terminal Tcc and the ground voltage terminal Tss. The PMOS transistor 14 has a source electrode connected with the power supply voltage terminal Tcc, a drain electrode connected with the second node N2, and a gate electrode connected with the second node N2. That is, the PMOS transistor 11 is diode-connected, and the PMOS transistors 11 and 14 constitute a first current mirror circuit. The NMOS transistor 15 has a source electrode connected with the ground voltage terminal Tss through the resistance element 16, a drain electrode connected with the second node N2, and a gate electrode connected with the third node N3. That is, the NMOS transistors 13 and 15 constitute a second current mirror circuit. Furthermore, the voltage generator 10 has a PMOS transistor 17 between the power supply voltage terminal Tcc and the node N2. The conductive state of the PMOS transistor 17 is controlled by an inverted signal STBb of a standby mode signal STB. The standby mode signal STB is externally input to the bias circuit. When the bias circuit operates normally, a first bias voltage Vb1 is output from the node N2 and a second bias voltage Vb2 is output from the node N3.
The start-up circuit 20 has a PMOS transistor 21 connected between the power supply voltage terminal Tcc and a voltage dividing node Nd and diode-connected NMOS transistors 22 and 23 connected in series between the voltage dividing node Nd and the ground voltage terminal Tss. The conductive state of the PMOS transistor 21 is controlled by the standby mode signal STB. Furthermore, the start-up circuit 20 has a diode 24 connected between the voltage dividing node Nd and the first node N1 of the voltage generator 10. The diode 24 has an anode connected with the voltage dividing node Nd and a cathode connected with the first node N1. The standby mode signal STB is inverted by an inverter 25, and then the inverted standby mode signal STBb is applied to a gate electrode of the PMOS transistor 17.
Details of the operations with respect to the above-mentioned circuits are described below.
When the bias circuit starts, that is, during a start-up process of the bias circuit, the power supply voltage Vcc is applied to the power supply voltage terminal Tcc with the level of the standby mode signal STB initially kept in a “Low” (hereinafter referred to as “L”) level. Then, the PMOS transistor 17 is turned OFF and the PMOS transistor 21 is turned ON. After that, an electrical current passes through the diode-connected NMOS transistors 22 and 23, and then an electrical potential rises on the voltage dividing node Nd. Since the PMOS and NMOS transistors of the voltage generator 10 is kept OFF just after the bias circuit starts, the electrical potential on the voltage dividing node Nd becomes higher than that on the first node N1. Thereby, an electrical current passes through the diode 24 from the voltage dividing node Nd toward the first node N1.
The electrical current flowing into the first node N1 is passed through the resistance element 12 and the NMOS transistor 13 toward the ground voltage terminal. In accordance with the electrical current passing through the NMOS transistor 13, the second current mirror circuit generates an electrical current passing through the NMOS transistor 15. That is, the electrical current whose amount depends on the value of the resistance element 16 passes through the PMOS transistor 14, NMOS transistor 15 and resistance element 16 from the power supply voltage terminal Tcc toward the ground voltage terminal Tss. In addition, based on the electrical current passing through the PMOS transistor 14, the first current mirror circuit generates an electrical current passing through the PMOS transistor 11. Then, the electrical potential on the first node N1 is raised. When the electrical potential difference between the first node N1 and the voltage dividing node Nd becomes lower than a forward-biased voltage, the diode 24 does not allow the electrical current to flow. Consequently, an electrical potential on the second node N2 becomes lower than the power supply voltage Vcc by approximately 1V, and is output from the voltage generator 10 as the first bias voltage Vb1. An electrical potential on the third node N3 becomes higher than the ground voltage Vss by approximately 1V, and is output from the voltage generator 10 as the second bias voltage Vb2. After that, the bias circuit operates normally.
When the bias circuit operates in a standby mode (a low power consumption mode) after the above-mentioned normal operation mode, the level of the standby mode signal STB turns to a “High” (hereinafter referred to as “H”) level. With this change in the level of the standby mode signal STB, the PMOS transistor 17 is turned ON and the PMOS transistor 21 is turned OFF. With the PMOS transistor 21 turned OFF, the electrical current is prevented from passing through the PMOS transistor 21 and the NMOS transistors 22 and 23. On the other hand, with the PMOS transistor 17 turned ON, the PMOS transistors 11 and 14 are turned OFF and the electrical current is prevented from passing through the PMOS transistors 11 and 14. Hereby, the electrical current is also prevented from passing through the NMOS transistors 13 and 15. At this time, the first bias voltage Vb1 becomes approximately the power supply voltage Vcc. As mentioned above, since the bias circuit does not allow the electrical current to pass through the PMOS transistor 21 and the NMOS transistors 22 and 23 in the standby mode, a low power consumption is realized in this bias circuit.
In addition, to further decrease power consumption, a bias circuit has been proposed as described in Document 1 (Japanese Patent Publication Laid-open No. 2001-326535). The bias circuit as described in the Document 1, whose circuit configuration and principle of operation are different from that in the above-mentioned prior art, reduces the consumption of the electrical current in the start-up circuit by using a standby mode signal in the standby mode.
However, in the bias circuit as described above, since the PMOS transistor 21 is turned ON even after the power supply voltage Vcc is stable, the electrical current passes through the PMOS transistor 21 and diode-connected NMOS transistors 22 and 23 in the start-up circuit 20 during the normal operation mode as well as during the start-up process of the bias circuit.
In order to decrease the electrical current passing through the start-up circuit 20 in the normal operation mode, it can be proposed that an ON-state resistance of the PMOS transistor 21 is made greater. In this case, however, it takes a long time to stably output the first and second bias voltages Vref1 and Vref2. That is, since start-up of the bias circuit is slower, it is not effective that the ON-state resistance of the PMOS transistor 21 is merely made greater in order to decrease the power consumption in the start-up circuit 20 in the normal operation mode.
On the other hand, if the above electrical current is completely cut off by turning OFF the PMOS transistor 21 in the start-up circuit 20 in the normal operation mode, the power consumption in the start-up circuit 20 can be decreased. In this case, however, the voltage dividing node Nd becomes electrically unstable. That is, a possibility arises of changing the electrical potential on the voltage dividing node Nd because of a signal transmitting in a peripheral circuit arranged near the bias circuit. For example, an output circuit of a Liquid Crystal Display (hereinafter referred to as “LCD”) driver circuit, which operates by a voltage higher than the power supply voltage Vcc, can be taken as the peripheral circuit. If the electrical potential would increase on the voltage dividing node Nd, an electrical current flows from the voltage dividing node Nd to the first node N1 through the diode 24. Then, the first and second bias voltages Vb1 and Vb2 are changed. As a result, a malfunction can occur in a circuit into which the first or second bias voltages Vb1 and Vb2 are input. Therefore, it is desired in the bias circuit that the reference voltage can be quickly output during the start-up process of the bias circuit and that the power consumption can be decreased during the normal operation mode while the bias voltages are stably output.